SN74LVC2G04DBVR
UMW · Logic
VerifiedFAE reviewed
| Parameter | SN74LVC2G04DBVR | SN74LVC2G04DBVR | Engineering note |
|---|---|---|---|
| Recommended operating temperature | -40 C to +125 C | -40 C to +85 C in the Recommended Operating Conditions table | The target electrical-table heading also shows -55 C to +125 C, which conflicts with its recommended range. The conservative recommended limit of +85 C is used for this review. |
| Maximum propagation delay at VCC = 3.3 V | 4.6 ns over -40 C to +125 C | 6.5 ns for RL = 1 Mohm and CL = 15 pF | The target is slower in the published maximum delay and is not interchangeable in timing-margin-critical paths without recalculation. |
| Input leakage current | +/-5 uA maximum | +/-1 uA maximum | The target publishes a tighter leakage limit. |
| ESD ratings | 2000 V HBM and 1000 V CDM | 2000 V HBM, 200 V machine model, and CDM marked N/A | The reviewed target document does not establish CDM equivalence. |
FAE documentary review accepted for the exact TI and UMW SN74LVC2G04DBVR order codes. Both are dual inverters in SOT-23-6 with the same 1A/GND/2A/2Y/VCC/1Y pin functions, 1.65 V to 5.5 V supply, 24 mA drive at 3.3 V and 3000-piece tape and reel. The target is limited to +85 C by its recommended operating table, has higher maximum propagation delay and does not publish a CDM rating. Document review only; not bench, reliability or production qualified.
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