GD32F407VET6
GigaDevice · MCU
VerifiedFAE reviewed
| Parameter | STM32F407VET6 | GD32F407VET6 | Engineering note |
|---|---|---|---|
| Package and pin sequence | STM32F407VET6: LQFP100, 14 x 14 mm | GD32F407VET6: LQFP100, 14 x 14 mm, green industrial | The exact order codes are both LQFP100. Table-based comparison found the same physical pin names on 1 through 100 except ST VCAP_1/VCAP_2 at pins 49/73, which the GD table marks NC. |
| External VCAP pins | VCAP_1 on pin 49 and VCAP_2 on pin 73 | Pins 49 and 73 are marked NC | Remove or independently assess ST-oriented VCAP capacitors and regulator/reset circuitry. The physical land positions align, but the electrical function of these pins is not identical. |
| Operating supply voltage | 1.8 V to 3.6 V | 2.6 V to 3.6 V | The target minimum supply is 0.8 V higher. Designs operating below 2.6 V are not eligible for this replacement. |
| Flash and SRAM | 512 KB Flash and 192 KB SRAM | 512 KB code Flash and 192 KB SRAM | The main code/Flash and SRAM capacities correspond for the VE grade. Flash-latency, wait-state, option-byte and memory-map behavior still require target-specific firmware configuration. |
| Peripheral identifiers and software | STM32 TIMx, SPIx, I2Cx, USARTx register and firmware ecosystem | GD32 TIMERx, SPIx, I2Cx, USARTx register and firmware ecosystem | The pin functions and package positions largely align, but peripheral numbering, registers, clock setup, USB/Ethernet behavior, drivers and tool support differ. |
FAE documentary review accepted for the exact STM32F407VET6 and GD32F407VET6 order codes. Both are 512 KB Flash, 192 KB SRAM, 82-GPIO, 168 MHz LQFP100 Cortex-M4 MCUs rated -40 C to +85 C. The complete pin table matches except ST VCAP_1/VCAP_2 at LQFP100 pins 49/73, where GD marks NC. The target minimum supply rises from 1.8 V to 2.6 V. Pin correspondence does not establish register, clock, USB, Ethernet, driver or software compatibility. Document review only; not bench, temperature-cycle, EMC, reliability or production qualified.
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