P24C08C-SSH-MIR
Puya · Memory
VerifiedFAE reviewed
| Parameter | AT24C08C-SSHM-T | P24C08C-SSH-MIR | Engineering note |
|---|---|---|---|
| Package and exact order code | AT24C08C-SSHM-T: 8-lead JEDEC SOIC, tape and reel; 8 Kbit (1,024 x 8) | P24C08C-SSH-MIR: SOP8 150 mil, RoHS/halogen-free, industrial temperature, tape and reel; 8 Kbit (1,024 x 8) | Both exact codes use a standard 8-lead I2C EEPROM footprint and a nominal 1.27 mm lead pitch. Microchip calls the package SOIC while Puya calls it SOP; the final land pattern and assembly tolerances require board-level release checks. |
| Memory organization and normal-area protocol | 1,024 x 8, 16-byte page write, one-byte word address and 1010b + A2/A9/A8 normal-area device address | 1,024 x 8, 16-byte page write, one-byte word address and 1010b + E2/A9/A8 normal-area device address | The normal memory protocol, address capacity and partial-page-write behavior correspond. The target pin-7 name is WCB rather than WP, but both are high-active write inhibits. Puya additionally provides a lockable 16-byte ID page and a 128-bit serial number. |
| Supply, speed and standby current | 1.7 V to 5.5 V and -40 C to +85 C; 1 MHz Fast-mode Plus is specified for 2.5 V to 5.5 V; 6 uA maximum standby at 5.5 V | 1.7 V to 5.5 V and -40 C to +85 C; 400 kHz and 1 MHz are specified across 1.7 V to 5.5 V; 4 uA maximum standby at 5.5 V | The target speed and standby specifications are equal or better. Bus rise time, pull-up sizing and timing margin must still be checked over the actual supply and temperature range. |
| Endurance and retention | 1,000,000 write cycles characterized at 25 C and 100-year retention at 55 C | 1,000,000 write cycles characterized at 25 C and 100-year retention at 55 C | The documented endurance and retention figures correspond. These are datasheet characterization limits, not a production qualification of the target assembly or application write pattern. |
FAE documentary review accepted for the exact Microchip AT24C08C-SSHM-T and Puya P24C08C-SSH-MIR order codes. Both are 8 Kbit, 1,024 x 8 I2C EEPROMs in a standard 8-lead 1.27 mm-pitch SOIC/SOP package, rated 1.7 V to 5.5 V and -40 C to +85 C, with 16-byte pages, a one-byte word address, 5 ms maximum self-timed writes, one million write cycles and 100-year retention. The normal-area protocol and high-active write inhibit correspond; the target adds an ID page and serial number. Document review only; no bench, temperature-cycle, EMC, reliability or production qualification was performed.
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