P24C512H-SSH-MIR
Puya · Memory
VerifiedFAE reviewed
| Parameter | AT24C512C-SSHM-T | P24C512H-SSH-MIR | Engineering note |
|---|---|---|---|
| Additional command set | No dedicated identification page or serial-number command | 128-byte write-lockable identification page and 128-bit serial number | Target-only features outside the normal memory array; existing normal-memory accesses remain compatible. |
| Maximum clock frequency | 1 MHz Fast Mode Plus only at 2.5-5.5 V; 400 kHz at 1.7-5.5 V | 1 MHz at 1.7-5.5 V; 2 MHz high-speed mode supported | The target has a higher documented clock ceiling at low voltage. |
| Write endurance | 1,000,000 cycles | 10,000,000 cycles | Target endurance is higher in the manufacturer datasheet. |
Accepted after primary-datasheet review: both exact order codes are 512 Kbit, 8-lead SOIC/SOP 150 mil, 128-byte page, two-byte word address, 1.7-5.5 V and -40 to +85 °C. Both use 1010b + A2/A1/A0 and a high-active write inhibit on pin 7. PUYA additionally provides transparent ECC, an identification page and a 128-bit serial number. HuluIC has an exact model record but no current stock shown for P24C512H-SSH-MIR, so no stock or price claim is made. Document review only; not bench, reliability or production qualified.
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